ADM1029
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8
Functional Description
Serial Bus Interface
Control of the ADM1029 is carried out via the serial bus.
The ADM1029 is connected to this bus as a slave device,
under the control of a master device.
The ADM1029 has a 7-bit serial bus address. The four
MSBs of the address are set to 0101. The three LSBs can be
set by the user to give a total of eight different addresses,
allowing up to eight ADM1029s to be connected to a single
serial bus segment.
To minimize device pin count and size, the three LSBs are
set using a single pin (ADD, Pin 15). This is an 8-level input
whose input voltage is set by a potential divider. The voltage
on ADD is sampled immediately after power-up and
digitized by the on-chip ADC to determine the value of the
3 LSBs. Since ADD is sampled only at power-up, any
changes made while power is on will have no effect.
Figure 16. Setting the Serial Address
ADM1029
ADD
V
CC
GND
R1
R2
Table 5 shows resistor values for setting the 3 LSBs of the
serial bus address. The same principle is used to set the
voltage on Pin 18 (TMIN/INSTALL), which controls the
automatic fan speed control function, and also tells the
ADM1029 how many fans should be installed, as described
later.
If several ADM1029s are used in a system, their ADD
inputs can tap off a single potential divider, as shown in
Figure 17.
Figure 17. Setting Address of up to Eight ADM1029s
ADM1029#1
ADD
V
CC
GND
ADDRESS XXXX111
1.5 kW
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADM1029#2
ADM1029#3
ADM1029#4
ADM1029#5
ADM1029#6
ADM1029#7
ADM1029#8
ADDRESS XXXX110
1 kW
ADDRESS XXXX101
1 kW
ADDRESS XXXX100
1 kW
ADDRESS XXXX011
1 kW
ADDRESS XXXX010
1 kW
ADDRESS XXXX001
1.5 kW
ADDRESS XXXX000
Table 5. RESISTOR RATIOS FOR SETTING SERIAL BUS ADDRESS
3 MSBs of ADC
Ideal Ratio
R2/(R1 + R2)
R1 (kW)
R2 (kW)
Actual
R2/(R1 + R2)
Error (%)
Address
111
N/A
0
?/DIV>
1
0
0101111
110
0.8125
18
82
0.82
+0.75
0101110
101
0.6875
22
47
0.6812
0.63
0101101
100
0.5625
12
15
0.5556
0.69
0101100
011
0.4375
15
12
0.4444
+0.69
0101011
010
0.3125
47
22
0.3188
+0.63
0101010
001
0.1875
82
18
0.18
0.75
0101001
000
N/A
?/DIV>
0
0
0
0101000
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
START condition, defined as a high-to-low
transition on the serial data line SDA, while the
serial clock line SCL remains high. This indicates
that an address/data stream will follow. All slave
peripherals connected to the serial bus respond to
the START condition, and shift in the next eight
bits, consisting of a 7-bit address (MSB first) plus
an R/W
bit, which determines the direction of the
data transfer, i.e., whether data will be written to
or read from the slave device.
The peripheral whose address corresponds to the
transmitted address responds by pulling the data
line low during the low period before the ninth
clock pulse, known as the Acknowledge Bit. All
other devices on the bus now remain idle while the
selected device waits for data to be read from or
written to it. If the R/W
bit is a 0, the master will
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